1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device using a film for forming a protective layer in which a support base, an adhesive layer, and a thermosetting resin layer are laminated, in this order.
2. Description of Related Art
Conventionally, because the distance between circuits is becoming shorter as the circuit pattern formed on a semiconductor chip is becoming finer, the capacitance between adjacent circuits is becoming greater. A phenomenon occurs according to which a signal traveling in the circuit becomes slow (signal delay) in proportion to the increase in capacitance. It has been proposed to lower the capacitance between circuits by forming a low dielectric material layer on the circuit using a material having a low dielectric constant, a so-called low-k material (low dielectric material).
Examples of the low dielectric material layer include a SiO2 film (relative permittivity k=4.2), a SiOF film (k=3.5 to 3.7), and a SiOC film (k=2.5 to 2.8). Such a low dielectric material layer is formed on a semiconductor wafer by a plasma CVD method, for example.
However, such a low dielectric material layer is very brittle, and may cause cracks in a dicing step of the semiconductor process and operational abnormality of the semiconductor element. A method of removing the low dielectric material layer first using a laser (laser scribing) and then dicing the material with a blade or the like has been employed recently (see Japanese Patent Application Laid-Open No. 2010-093273, for example).